High-throughput dual-mode single/double binary MAP processor design for wireless WAN,” submission to

In this paper we present the VLSI implementation of a high-throughput enhanced Max-log-MAP processor that supports both single-binary (SB) and double-binary (DB) convolutional turbo codes. The combined hybrid-window (HW) and parallel-window (PW) MAP decoding is introduced to support arbitrary frame sizes with high throughput. A 1.28 mm2 dual-mode (SB/DB) 2PW-1HW MAP processor is also implemented in TSMC 0.13ȝm CMOS process to verify the proposed approaches. The proposed MAP processor can be used as hardware accelerators in multistandard platform for wireless WAN with low cost and low energy. Index Terms—hardware accelerators, turbo codes, maximum a-posteriori probability. 1